Integrated circuits may include many components, and each of the components may operate from and/or be synchronized with a clock signal. When the clock signal becomes unavailable, the components may fail to operate and/or fall out of synchronization. The integrated circuits then begin producing erroneous output and eventually cease operating. For example, when the output of one component is communicated to the input of another component, the two components may be synchronized such that the second component knows when the first component has output data intended for reading by the second component.
A phase-locked loop (PLL) is one component that operates from a clock signal. The phase-locked loop (PLL) receives an input clock signal and generates a clock signal that may be used to operate and/or synchronize other components. In particular, a phase-locked loop (PLL) generates an output clock with a phase and/or frequency that has a determined relationship to an input clock's phase and frequency, such as the master clock's phase and frequency. The output clock signal from the phase-locked loop (PLL) may be used to operate, for example, audio components such as an audio amplifier.
FIG. 1 is a block diagram illustrating a conventional phase-locked loop (PLL). A phase-locked loop (PLL) 100 may include a phase-frequency detector (PFD) 102, which receives a master clock signal MCLK. A charge pump 104 and a loop filter 106 are coupled to the phase-frequency detector (PFD) 102 to condition an output of the phase-frequency detector (PFD) 102 for input to a voltage-controlled oscillator (VCO) 108. The oscillator 108 generates a clock signal, such as a square wave, based on the input to the oscillator 108 from the phase-frequency detector (PFD) 102, the charge pump 104, and the loop filter 106. A divider 110 closes a feedback loop from the oscillator 108 to the phase-frequency detector (PFD) 102. The divider 110 may allow the oscillator 108 to generate a different frequency clock signal than the clock frequency of the master clock input signal MCLK.
The oscillator 108 is dependent upon the master clock input signal MCLK. If the master clock signal input MCLK disappears, then the phase-locked loop 100 will cease functioning correctly. Before the oscillator 108 entirely shuts down, the oscillator 108 may generate an incorrect clock signal output. Components receiving the incorrect clock signal output may then also generate erroneous output. For example, if audio components are operating from the output clock signal of the oscillator 108, then the audio components may generate undesirable noise from a speaker when the master clock signal input MCLK disappears.
The master clock signal input MCLK may disappear due to, for example, glitches in other components coupled to the phase-locked loop (PLL) 100, a malfunction in the system that generates the master clock, or an external broken link in the master clock distribution network. Regardless of the reason for the loss of the master clock signal input MCLK, it is undesirable that the phase-locked loop (PLL) 100 generate an erroneous clock signal output that may negatively impact components, such as the audio components.
One conventional solution is to open the phase-locked loop (PLL) 100 by disconnecting the voltage-controlled oscillator 108 from the charge pump 104 when the master clock input signal MCLK disappears. After disconnecting the oscillator 108, a fixed voltage input may be provided to the oscillator 108 to allow the oscillator 108 to continue to output a clock signal. However, the fixed voltage input to the oscillator 108 will produce a different frequency output signal than that generated when the phase-locked loop (PLL) 100 is closed and providing input to the oscillator 108.
A conventional phase-locked loop (PLL) may attempt to set a fixed voltage at the input to the oscillator 108 similar to the voltage level at the oscillator 108 before the master clock input signal MCLK disappears. However, the voltage level will have changed before the phase-locked loop (PLL) can determine the master clock input signal MCLK has disappeared. Thus, the voltage level locked and input to the oscillator 108 will not be the needed voltage level to hold the oscillator 108 at the desired frequency.
Shortcomings mentioned here are only representative and are included simply to highlight that a need exists for improved phase-locked loops (PLLs), particularly for consumer-level devices. Embodiments described here address certain shortcomings but not necessarily each and every one described here or known in the art.